The present invention relates in general to semiconductor device fabrication methods and resulting structures. More specifically, the present invention relates to fabrication methods and resulting structures for a semiconductor device having stacked nanosheets with a wrap-around inner spacer.
In contemporary semiconductor device fabrication processes a large number of semiconductor devices, such as field effect transistors (FETs), are fabricated on a single wafer. FETs employ semiconductor fins to introduce on-wafer topography. With growing challenges in maintaining physical gate-length scaling and device performance tradeoff, extending the technology roadmap with lateral devices to and beyond the 10 nm technology node is becoming increasingly difficult. Non-planar device architectures, such as vertical fin and nanosheet FET devices, result in increased device density over lateral devices.